Cpld code

Modified from LVD's A600_8mb 4 * 1Mx16 dram verilog to use one 4Mx16 chip
notes: See also main page. Newer "cdtv" code needs config-in line state "high"

Version 20.1.2020 (untested)
source
"42Xe" for v42 & 5volt cpld

Version 7.4.2019 (some testing/trying out done)
source
"5i8d" for v5x, config-in
"5o8d" for v5x, config-out
"5f8d" for v5x, force config after one other, config-out
"6f8d" for v6x, force config after one other
8.4.2020 New: "6x8d" for v6x, try 8 or 4 + 2 meg configs, but not 1 meg

Version 28.3.2019
like 26.3.2019, for v5x,4x boards - untested
source
"40Xb" for v40, 5V XC9572, programmable grounds
"42Lb" for v42,43 XC9572XL
possibly not working:
"5xIb" for v5x, config-in
"5xOb" for v5x, config-out
"5xFb" for v5x, force config after one other, config-out


Version 26.3.2019
8.4.2020 note: 1 meg ram config block won't work when newer kickstart would try to place it at Axxxxx space (only 2xxxxx - 9xxxxx supported)
Beginning of /UDS Upper data strobe clocks autoconfig state machine. Recode dram control sequence (dram output on through 68k state S7, end to S0).
source
"6x8b" for v6x boards
"6x6b" for v6x boards 4+2 megs
"6xFb" for v6x boards, force-config-after-one-other

Version 14.2.2019
Clocking memory address comparator result to a register with address strobe seems to save logic resources.
source
"6x8a" for v6x boards, 8 megs
"6x6a" 4+2 megs
"6x4a" 4 megs
"5o8a" 5x boards, config-out, 8 megs
"5o6a" 4+2 megs
"5o4a" 4 megs

Version 19.1.2019
Reset signal filter. Logic starts to be full, without optimising further.
source
"6x19"for v6x boards
"6x2S"force config after on other (cdtv).v6x pcb
"5x2S"same for v5x, config/led -out

Version 17.12.2018
8/4+2+1 meg chained config offerings These two tested so much that config-out led lights.
source "6x17"
source config-out v5x "5xOO"

Version 16.12.2018
source 4+2 (but not +1 due to source bug) (almost same as 28.10.2018)
"6x7M" Skip offer 8 megs, try config 4 + 2 (but not + 1) megs
mem68k-161218-4meg.abl only 4megs offer
"6x4M" Skip offer 8 megs, try config 4 megs, no 2 or 1 meg blocks

Version 28.10.2018 - 6x28 "tested" - v5x board versions not working?
v5x version maybe turns 245 buffers off too early on writes? 8/4+2(bug: no +1) meg configuration (offer 8 meg first, if shutdown offer 4 + 2 (no +1))
new skip one config version: force autoconfig after one other config while config-in inactive high.
"rfsh_ras" possible glitch removed?
source
"6x28" for v6x boards
"6x1S" force skip one autoconfig before responding to E80000 (CDTV?), config right away if config-in low
"6SPS" Special, skip one autoconfig, (try config 8/4+2 but no+1) / 28.0000-9f.ffff RAM responding regardless of autoconfig
"5xOS" Not working- v58/59 boards, skip one autoconfig, config-out signal
"5xO2" Not working- config-out signal
"5xI2" Not working- config-out signal
"42L2" v42/43 XC9572XL tqfp100
"42C2" v42/43 5 volt XC9572
"40C2" V40 5 volt XC9572
JP3 spare signal 1 can be high. spare signal 2 probably driven low by "programmable grounds" option.

Version 23.9.2018 - mostly untested
Options: config 8 or 4+2 megs / only 4+2 megs - skip 1 autoconfiguration for CDTV - ram on regardless of autoconfig
In this "skip one autoconfig" version, config in must be active low. note 11.10.2018: possible race condition glitch at refresh signal? source
"6x6x" for v6x boards
"6xS1" skip one autoconfig before responding to E80000 (CDTV?)
"6xSP" note 11.10.2018 broken code - shouldn't work: Special, skip one autoconfig, try config 4+2 MB, 28.0000(or 30.0000?)-9f.ffff RAM responding regardless of autoconfig
"5xSO" v58/59 boards, skip one autoconfig, config-out signal
"5xCO" config-out signal
"5xCI" config-out signal
"42XL" v42/43 XC9572XL tqfp100
"42XC" v42/43 5 volt XC9572
"40XC" V40 5 volt XC9572
In these V4x codes, JP3 spare-signals do nothing.



In most codes below, autoconfig is likely broken especially config out.

Version 20.9.2018, from version 8.7.2018 1)
To bug fix restarting 68hc000 issue, removed rfsh_cas.aclr=!cpu_nas.pin; interfering refresh at a bad time?
Autoconfig bug can remain: For autoconfig out, line
when (!cpu_r_w.pin & ([a23..a16].pin == ^hE8) & ([a6..a3].pin == [1,0,0,1]) & autoconfig_started.fb) // write at $E80048..$E8004E
should probably be
when (!cpu_r_w.pin & ([a23..a16].pin == ^hE8) & ([a6..a1].pin == [1,0,0,1,0,0]) & autoconfig_started.fb) // write at $E80048
because Amiga could write to E8004A for low nybble of base address before writing to E80048(?) source V6X "2096" V5X "209I" config-in V5X "209O" config-out
V4x boards: JUMPER "sparepin1"(=driven logic high) to "sparepin2"(input), not to be left floating, logic low on JP3 center pin "sparepin2" should make ram appear at 200000 onwards regardless of autoconfig.
V42/43 XC9572XL "209L" V42/43 XC9572 "209C" V40 (XC9572) "2094"

12.9.2018 Abel version codes below buggy, (many times) don't work on v6x or v4x boards. (rfsh_cas issue)
Possibly verilog a few versions work better
Quick fix for v6x boards made from v4x board verilog code Version 05.06.2017
.jed, user code "v6xv" verilog source .ucf pin file for v6x boards

(buggy) Versions 8.7.2018, for v6x (both config in and out)
1) ABEL source 8 meg autoconfig for v6x boards, user code "v6x1"
2) 8meg ram on regardless of autoconfig, modified from version 29.12.2017 to v6x boards ABEL source 'R682' 8 meg, ram on regardless of autoconfig, user code "R683"

(buggy) Version 29.12.2017, for v5x, auto-config in (can be left unconnected with pull up resistor), ram on without autoconfig (can be added to AmigaOS by 'addmem'-command) ABEL source 8 meg, config in, ram on regardless of autoconfig

(buggy) Version 4.12.2017 ABEL source .jed: PCB V59/58 xc9572xl-vq64 8MB (auto)config out user code "O582" 4MB(*) config out "O542" 8MB config in "I582" 4MB(*) config in "I542" PCB v40/42/43 xc9572-tq100 8MB "XC82" 4MB(*) "XC42" PCB V42/43 xc9572xl-tq100 8MB "XL82" 4MB(*) "XL42"
(*)RAM only at $200000..5FFFFF, no autoconfig elsewhere in this cpld code version.

(buggy) Version 14.08.2017, abel hdl code, user codes for v40, v42/43, v58 "40a1", "42a1", "58a1": (pcb v59 uses same) ABEL source .jed: PCB v40/42 xc9572-tq100 "40a1" PCB V42 xc9572xl-tq100 "42a1" PCB V58 xc9572xl-vq64 "58a1"

Version 16.06.2017, cpld user code "1606", v42 pcb, 3.3V xc9572xl-tq100: verilog code is same as version 0506 ucf pin list, v42 pcb .jed for xc9572xl

Version 05.06.2017, cpld user code "0506", for v40 and V42 pcb, 5 volt xc9572-tq100: verilog ucf pin list .jed for xc9572

Version 19.04.2017, cpld user code "1904", v40 pcb: verilog ucf pin list .jed for xc9572

(bugged) Version 30.03.2017, cpld user code "3003",initial release version, pcb v40, likely doesn't work on a lot of A500 mainboards, but worked on a special test main board (timing of clock signal maybe was the issue): verilog ucf pin list .jed